Semiconductor Engineering

Overcoming Shallow Trench Isolation

To prevent electrical current leaking between adjacent transistors, state-of-the-art microchips feature shallow trench isolation (STI) to isolate transistors from each other. Key steps in the STI ...
EDN

Models for high-voltage transistors in a standard CMOS process

Designers of electronics and communications systems are constantly faced with the challenge of integrating greater functionality on less silicon area. Many of the system blocks – such as power ...
EDN

Renesas Claims Faster, Lower Power SOI CMOS

Japanese memory chipmaker Renesas Technology Corp. said today it has developed silicon-on-insulator (SOI) CMOS device technology that is both faster and operates at a lower voltage than standard SOI ...
Electronic Design

BiCom-III Process Triples Speed, Halves Noise

Dubbed BiCOM-III, TI's recently announced silicon-germanium (SiGe) complementary bipolar-CMOS manufacturing process integrates both NPN- and PNP-type bi-polar transistors. The result of this ...