Semiconductor Engineering

Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity

The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...
Design-Reuse

Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol

Avery to offer VIP, verification aids to enable design with recently-announced die-to-die interface standard backed by industry leaders Tewksbury, MA – June 15, 2022 – Avery Design Systems, a leader ...
Semiconductor Engineering

Bringing RFIC Design And Verification Into The Modern Era

For decades, developers of radio frequency (RF) chips and other analog/mixed-signal (AMS) integrated circuits (ICs) have used traditional techniques for design and verification. Most RFIC designers ...
Design-Reuse

Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)

SoC (System-on-Chip) Verification effort mainly includes three key phases: Planning, Development and Verification. Planning phase includes preparing verification strategy in terms of Test plan, ...