EDN

How to Manage Clock Jitter Noise for Accurate Timing Sign-off

With shrinking process nodes and increasing operating frequencies, designers face the challenges of managing noise caused by signal crosstalk and dynamic voltage drop to meet their timing requirements ...
Design-Reuse

Extreme DA and ATopTech Announce Partnership for Timing Sign-off Closure

Santa Clara, Calif. – May 26, 2011 -- Extreme DA, the leader in new-generation timing analysis software and ATopTech, Inc., the leader in next generation physical design solutions, today announced a ...
Business Wire

TSMC Reference Flow 9.0 Covers Extreme GoldTime Sign-off Timing Analysis

SANTA CLARA, Calif.--(BUSINESS WIRE)--Extreme DA ™ today announced that TSMC Reference Flow 9.0 covers the GoldTime ™ Statistical timing analyzer. Supporting 40nm process technology, Reference Flow ...
Design-Reuse

Timing Closure in the FinFET Era

Achieving system-on-chip (SoC) timing closure is a major obstacle in the FinFET era. Even though designers can now use faster transistors that consume and leak less power than before, FinFET ...